An overview of known completion-detection methods is given and their a
dvantages and drawbacks are briefly discussed. A relatively new class
of single-rail completion-detection techniques is considered in more d
etail and simulation results based on adder implementations are presen
ted. A variant of a single-rail technique, which has the advantage of
glitch-suppression and robust operation, is introduced. Simulation res
ults are provided, based on a physical layout of the circuit with extr
acted parasitics.