A FULLY DEPLETED CMOS SIMOX LSI SCHEME USING LVTTL-COMPATIBLE AND OVER-2,000-V ESD-HARDNESS I/O CIRCUIT FOR REDUCTION IN ACTIVE AND STATIC POWER-CONSUMPTION/

In a fully depleted (FD) CMOS/SIMOX device, the threshold voltage can be reduced by 0.1 V while keeping the same off current as that of bulk CMOS. This enhances gate speed at low supply voltage so that lowering supply voltage reduces both active and static power consumption witho ut additional circuits. An LSI architecture featuring a low supply vol tage for internal gates and an LVTTL interface is proposed. However, t o implement the architecture with FD-CMOS/SIMOX devices, there were pr oblems which were low drain-breakdown voltage and half electrostatic d ischarge (ESD) hardness compared with that of bulk CMOS devices. An LV TTL-compatible output buffer circuit is developed to overcome the low drain-breakdown voltage. Cascade circuits are applied at an output sta ge and a voltage converter with cross-coupled PMOS is used for reducin g the applied voltage from 3.3 V to 2.2 V or less. Using this output b uffer together with an LVTTL-compatible input buffer, external 3.3 V s ignal can be converted from/to 2.0-1.2 V signal with little static cur rent. The cascade circuit, however, weakens the already low ESD hardne ss of the CMOS/SIMOX circuit. The new ESD protection circuit provides robust LVTTL compatible I/O circuits. It features lateral diodes worki ng as drain-well-diodes in bulk CMOS and protection devices for dual p ower supplies. A diode/MOS merged layout pattern is used for both to d issipate heal and save area. The CMOS/SIMOX ESD protection circuit is the first one to meet the MIL standard. Using 120 kgate test LSIs made on 300 kgate array with 0.25-mu m CMOS/SIMOX, 0.25-mu m bulk CMOS and 0.5-mu m bulk CMOS, power consumptions are compared. The 0.25-mu m CM OS/SIMOX LSI can operate at an internal voltage of 1.2 V at the same f requency as the 0.5-mu m LSI operating at 3.3 V. The internal supply v oltage reduction scheme reduces LSI power consumption to 3% of that of 0.5-mu m bulk LVTTL-LSI.