ANALYSIS OF THE DELAY DISTRIBUTIONS OF 0.5 MU-M SOI LSIS

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD a nd a self-aligned titanium silicide (TiSi2) source-drain structure. Th e advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divid er. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V . The SOI adder speed is about 1.3 times faster than the bulk adder. T he power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction cap acitance and little substrate bias effects, in addition to the low wir ing capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.