INVERTER REDUCTION ALGORITHM FOR SUPER FINE-GRAIN PARALLEL-PROCESSING

Authors
ITO H NAGAMI K SHIOZAWA T NAKAMURA Y
Citation
H. Ito et al., INVERTER REDUCTION ALGORITHM FOR SUPER FINE-GRAIN PARALLEL-PROCESSING, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(3), 1997, pp. 487-493
Citations number
13
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Information Systems
Journal title
IEICE transactions on fundamentals of electronics, communications and computer science → ACNP
ISSN journal
09168508
Volume
E80A
Issue
3
Year of publication
1997
Pages
487 - 493
Database
ISI
SICI code
0916-8508(1997)E80A:3<487:IRAFSF>2.0.ZU;2-6
Abstract
We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algor ithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and e valuate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.