A NEW SNUBBER CIRCUIT FOR HIGH-EFFICIENCY AND OVERVOLTAGE LIMITATION IN 3-LEVEL GTO INVERTERS

A new low-loss snubber circuit including an overvoltage clamping circu it for a three-level gate-turn-off (GTO) inverter is presented. The pr oposed snubber circuit is effective in restriction of the dv/dt and th e overvoltage values across each GTO at turnoff and the snubber loss i s less than half that of the conventional RCD snubber circuit. In addi tion, there is no blocking voltage balancing problem between the inner and outer GTO's that occurs in the case where a conventional RCD snub ber circuit is used in three-level inverter topology. Experimental res ults demonstrate that the proposed snubber circuit is very effective f or a large capacity three-level GTO inverter.