REALIZATION OF A NEURONAL HARDWARE WITH D IGITAL SIGNAL PROCESSOR ANDPROGRAMMABLE GATE ARRAYS

Authors
Citation
A. Meyerbase, REALIZATION OF A NEURONAL HARDWARE WITH D IGITAL SIGNAL PROCESSOR ANDPROGRAMMABLE GATE ARRAYS, Frequenz, 51(1-2), 1997, pp. 50-54
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
ISSN journal
00161136
Volume
51
Issue
1-2
Year of publication
1997
Pages
50 - 54
Database
ISI
SICI code
0016-1136(1997)51:1-2<50:ROANHW>2.0.ZU;2-V
Abstract
In this paper we describe how the processing speed of a radial basis n eural network can be performed by the use of field programmable gate a rrays (FPGA), The calculation of the very time-consuming exponential f unction is taken by an optimized CORDIC-processor. We determine the nu mber of the necessary FPGAs and do a processing speed comparison betwe en FPGA and DSP referring to an application in speech recognition.