ENHANCING MATRIX-METHOD TO DETECT LOGIC HAZARDS

A matrix method for the detection of static hazards in combinational l ogic circuits has been reported (Heal and Page 1993). The method gener ates 0 and 1-sets of all nodes in each gate level of a circuit progres sively until it reaches the output of the circuit. The sets generated are subsequently used to determine the existence of static hazards. Th is paper introduces enhancements to improve the capabilities and perfo rmances of the method, which is applicable to the detection of logic h azards in synchronous combinational logic circuits only. It is shown h ow certain matrix operations can be simplified to save storage and com putation time. A simpler way of determining static hazards is proposed . Required modifications of the method to incorporate the detection of dynamic hazards are presented. It is further shown that the algorithm can also be applied to the transient analysis of digital circuits wit h exclusive-OR (EX-OR) gates. Examples are given for illustration.