DESIGN OF AN ARRAY PROCESSOR FOR PARALLEL SKELETONIZATION OF IMAGES

Citation
N. Bourbakis et al., DESIGN OF AN ARRAY PROCESSOR FOR PARALLEL SKELETONIZATION OF IMAGES, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(4), 1997, pp. 284-298
Citations number
28
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
10577130
Volume
44
Issue
4
Year of publication
1997
Pages
284 - 298
Database
ISI
SICI code
1057-7130(1997)44:4<284:DOAAPF>2.0.ZU;2-0
Abstract
This paper presents the design, evaluation, and the implementation of an application specific array processor (ASAP) desirable for high spee d parallel skeletonization of binary images. The array processor recei ves the input image in a binary form and generates the skeleton of the nonzero regions (objects, or silhouettes) contained in the image in p arallel. In particular, each processing element (PE) of the array proc essor receives additional information from the neighboring PE's and ex ecutes independently its own algorithm by maintaining or zeroing its o wn value ''1'' for the final generation of the skeleton of the object, The skeletons produced by this array processor are: 1) region's size independent (nonsensitive in small variation of shape) and 2) sensitiv e to the region's shape, The ability of the array processor to produce these two types of skeleton makes it flexible for image processing ap plications such as handwritten character recognition under uncertainty (non sensitive skeleton), or detection of defects on printing circuit s (sensitive skeleton). A comparison of the proposed algorithm [parall el symmetric thinning algorithm (PSTA)] to a number of other parallel thinning algorithms is also provided indicating its advantages and dis advantages.