VLSI ON-CHIP INTERCONNECTION PERFORMANCE SIMULATIONS AND MEASUREMENTS

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or ''interconnects.'' Performa nce can be affected by wiring geometry, materials, and processing deta ils, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical pr operties, pulse propagation, and CPU cycle-time estimation, with parti cular attention to potential advantages of advanced materials and proc esses for wiring of high-performance CMOS microprocessors. Detailed pe rformance improvements are presented for migration to copper wiring, l ow-epsilon dielectrics, and scaled-up interconnects on the final level s for long-line signal propagation.