INTERCONNECT FABRICATION PROCESSES AND THE DEVELOPMENT OF LOW-COST WIRING FOR CMOS PRODUCTS

As the cost and performance of integrated circuit (IC) interconnection s, or ''interconnects,'' become increasingly important to the developm ent and manufacturing of successful advanced IC products, so also do u nderlying metallization and patterning processes. In particular, the g oals of achieving product design specifications, low development cost (high and early yield), low manufacturing cost, and portability across products can only result from applying robust unit processes that com bine to form integrable and scalable process modules. In this paper, w e review the interconnect fabrication processes used to form currently manufactured IBM CMOS products, and describe the materials and proces s integration issues that motivated their selection. In addition, we i dentify factors which may inhibit application of the fabrication proce sses to future products having smaller dimensions. The review suggests that large improvements in cost and scalability can be achieved by fo rming dual-damascene monolithic studs/wires. previously, the dual-dama scene approach was not generally applicable because of the lack of sui table metal deposition techniques for filling high-aspect-ratio featur es with highly conductive metal. However, recent advances may provide that capability both for near-term applications using Al-based wiring, and also for future applications using more extendible Cu-based wirin g.