FAST ALGORITHMS FOR SELECTION OF TEST NODES OF AN ANALOG CIRCUIT USING A GENERALIZED FAULT DICTIONARY APPROACH

Selection of test nodes is an important phase of the fault dictionary approach, It is demonstrated in this paper that the techniques used fo r this purpose in other approaches of analog fault diagnosis like faul t analysis and fault verification are not in general suitable for the fault dictionary approach, The ambiguity set is a simple and effective concept for choosing test nodes in the context of dictionaries, These sets are formed such that each faulty condition lies in only one ambi guity set. Deviating from this thinking, overlapping ambiguity sets ar e proposed in this paper, giving rise to a generalized fault dictionar y. These sets use information more fully and hence reduce the number o f test nodes. The concept of hashing is applied in this paper for sele cting test nodes, This gives a linear time algorithm (linear in the nu mber of fault voltage specifications f') and it is f' times faster tha n the existing methods. It is not possible to select test nodes faster than this. This technique can also be used to select test nodes by th e process of elimination of nodes. This is also linear in f' per node elimination. Even a group of nodes can be eliminated or selected withi n the same computation. This freedom is not possible with the existing methods.