ARCHITECTURAL SUPPORT FOR INTER-STREAM COMMUNICATION IN AN MSIMD SYSTEM

This paper considers hardware support for the exploitation of control parallelism on data parallel architectures. It is well known that data parallel algorithms may also possess control parallel structure. Howe ver, the splitting of control leads to data dependency and synchroniza tion issues that were implicitly handled in conventional SIMD architec tures. These include synchronization of access to scalar and parallel variables, and synchronization for parallel communication operations. We propose a sharing mechanism for scalar variables and identify a str ategy which allows synchronization of scalar variables between multipl e streams. The techniques considered are based on a bit-interleaved re gister file structure which allows fast copy between register sets. Ha rdware cost estimates and timing analyses are provided, and comparison with an alternate scheme is presented. The register file structure ha s been designed and simulated for the HP 0.8 mu m CMOS process, and ci rcuit simulation indicates access times are less than six nanoseconds. In addition, the impact of this structure on system performance is al so studied.