A NEW DFT METHODOLOGY FOR SEQUENTIAL-CIRCUITS

This paper introduce a new design for testability methodology for sequ ential circuits based on input/output pin utilization which exploits t he possibility of applying test patterns in parallel. The goal is to r educe the test application time maintaining the same fault coverage as the one obtained using full scan. The proposed procedure includes nec essary and sufficient conditions which are easily incorporated in a de sign system and produce the required implementation. Successful experi mental results are presented on benchmark circuits: IC test length is reduced on an average by 44% of full scan.