A NEW SCHEDULING ALGORITHM FOR SYNTHESIZING THE CONTROL BLOCKS OF CONTROL-DOMINATED CIRCUITS

This paper describes a new scheduling algorithm for automatic synthesi s of the control blocks of control-dominated circuits. The proposed sc heduling algorithm is distinctive in its approach to partition a contr ol/data now graph (CDFG) into an equivalent state transition graph. It works on the CDFG to exploit operation relocation, chaining, duplicat ion, and unification. The optimization goal is to schedule each execut ion path as fast as possible. Benchmark data shows that this approach achieved better results over the previous ones in terms of the speedup of the circuit and the number of states and transitions.