SIMULATING IC RELIABILITY WITH EMPHASIS ON PROCESS-FLAW RELATED EARLYFAILURES

A Monte-Carlo reliability simulator for integrated circuits (IC) that incorporates the effects of process-flaws, material properties, the ma sh layout, and use-conditions is presented. The mash layout is decompo sed into distinct objects, such as contiguous metal runs, vias, contac ts, and gate-oxides, far which user-defined distributors are used for determining the failure probability. These distributions are represent ed by a mixture of defect-related and wearout-related distributions. T he failure distributions for nets (sets of interconnected layout objec ts) are obtained by combining the distributions of their component obj ects. System reliability is obtained by applying control variate sampl ing to the logic network which is comprised of all nets. The effects o f k-out-of-n substructures within the reliability network are accounte d for, The methodology is illustrated by the effect of particulate-ind uced defects on metal rum and vials in a simple test circuit. The resu lts qualitatively verify the methodology and show that predictions whi ch incorporate failures due to process flaws are appreciably more pess imistic than those obtained from current practice. The methodology int roduces a computationally viable approach to building-in reliability d uring the design & fabrication stages, and accounts for infant mortali ty. application leverage has been enhanced by interfacing directly wit h commercially used CAD software, and by building the code around an e asily extended framework that allows the incremental addition of model s for more layout subsystems (eg, bonds, and gate oxides) as data beco me available.