A QUATERNARY PARTIAL-RESPONSE CLASS-IV TRANSCEIVER FOR 125 MBIT S DATA-TRANSMISSION OVER UNSHIELDED TWISTED-PAIR CABLES - PRINCIPLES OF OPERATION AND VLSI REALIZATION/

Citation
G. Cherubini et al., A QUATERNARY PARTIAL-RESPONSE CLASS-IV TRANSCEIVER FOR 125 MBIT S DATA-TRANSMISSION OVER UNSHIELDED TWISTED-PAIR CABLES - PRINCIPLES OF OPERATION AND VLSI REALIZATION/, IEEE journal on selected areas in communications, 13(9), 1995, pp. 1656-1669
Citations number
16
Categorie Soggetti
Telecommunications,"Engineering, Eletrical & Electronic
ISSN journal
07338716
Volume
13
Issue
9
Year of publication
1995
Pages
1656 - 1669
Database
ISI
SICI code
0733-8716(1995)13:9<1656:AQPCTF>2.0.ZU;2-W
Abstract
The paper describes an experimental transceiver for full-duplex transm ission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (Q PRIV) overall-channel signaling with near-end crosstalk (NEXT) cancell ation and maximum-likelihood sequence detection is employed. The spect ral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmit ter can be clocked independently, the receiver must cope with phase dr ift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital -to-analog conversion of transmit signals, analog-to-digital conversio n of receive signals, and adaptive NEXT cancellation are performed syn chronously with the transmitter clock. The rate change from transmit t iming to controlled receive timing is accomplished by an adaptive equa lizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maxim al phase drift of +/-100 ppm. The implementation of all digital signal -processing functions in a single 0.5 mu m CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power cons umption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements.