COMPUTING THE AREA VERSUS DELAY TRADE-OFF CURVES IN TECHNOLOGY MAPPING

We examine the problem of mapping a Boolean network using gates from a finite size cell library, The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary out puts, Our approach consists of two steps, In the first step,we compute delay functions (which capture gate area-arrival time tradeoffs) at a ll nodes in the network, and in the second step we generate the mappin g solution based on the computed delay functions and the required time s at the primary outputs. For a NAND-decomposed tree, subject to load calculation enters, this two-step approach finds the minimum area mapp ing satisfying a delay constraint if such solution exists, The algorit hm has polynomial run time on a node-balanced tree and is easily exten ded to mapping a directed acyclic graph (DAG), We also show how to acc ount for the wire delays during the delay function computation step, O ur results compare favorably with those of MIS2.2 mapper.