NEST - A NONENUMERATIVE TEST-GENERATION METHOD FOR PATH DELAY FAULTS IN COMBINATIONAL-CIRCUITS

Citation
I. Pomeranz et al., NEST - A NONENUMERATIVE TEST-GENERATION METHOD FOR PATH DELAY FAULTS IN COMBINATIONAL-CIRCUITS, IEEE transactions on computer-aided design of integrated circuits and systems, 14(12), 1995, pp. 1505-1515
Citations number
30
Categorie Soggetti
Computer Application, Chemistry & Engineering","Computer Science Hardware & Architecture
ISSN journal
02780070
Volume
14
Issue
12
Year of publication
1995
Pages
1505 - 1515
Database
ISI
SICI code
0278-0070(1995)14:12<1505:N-ANTM>2.0.ZU;2-S
Abstract
A test generation procedure for path delay faults is proposed that tar gets all path delay faults in the circuit-undertest. The procedure ove rcomes the difficulties in handling the exorbitant numbers of path del ay faults in practical circuits by using a nonenumerative method of co nsidering faults that never explicitly targets any specific path delay fault, Experimental results demonstrate the effectiveness of the meth od in deriving tests to detect very large numbers of path delay faults .