A NOVEL SCHEME TO REDUCE TEST APPLICATION TIME IN CIRCUITS WITH FULL SCAN

This paper proposes a hybrid method of combining sequential testing wi th scan testing in circuits with full scan capability. One shortcoming of full scan testing of sequential circuits is the high test applicat ion time. The goal of our scheme is to obtain shorter test application times while achieving detection of both the classical stuck-at faults as well as nonclassical faults such as delay faults. An algorithm for test generation in this hybrid scheme is described. Experimental resu lts demonstrating the effectiveness of our approach on ISCAS '89 seque ntial benchmark circuits are presented. Results for the stuck-at fault model and the transition fault model (which represents a simplified m odel for delay faults) are presented. Significant reduction in test ap plication time is shown possible.