ENSURING STRUCTURAL TESTABILITY OF HIGH-DENSITY SMT CIRCUIT PACKS

This paper overviews a ''next generation,'' end-to-end realization pro cess for circuit packs that enables reliable test access for structura l testing of aggressive, surface-mount technology (SMT) designs. New t est-access alternatives, such as boundary scan (B-S) and new fixturing techniques, are reviewed. Each stage of the process is examined relat ive to how final testability can be influenced. An overview of the sof tware systems and features needed to support this process, including c omputer-aided engineering/computer-aided design (CAE/CAD) tools, bound ary scan tools, and manufacturing/test data management systems, are pr esented.