HIGH-LEVEL SYNTHESIS OF DATA PATHS FOR EASY TESTABILITY

The paper presents a method for high-level synthesis of easy testable data paths from a given behavioural description of a design. The synth esis process uses an approach based on a problem-space genetic algorit hm (PSGA) to perform integrated scheduling, allocation of testable fun ctional units and registers under area, delay and testability constrai nts. Testability at behavioural level can be enhanced by minimising th e number of self-adjacent registers (self-loops). The main objective i s to minimise the testability overhead (area and delay) while searchin g the design-space to provide a self-loop free architecture. Experimen ts on benchmarks show that self-loops can be eliminated with minimum a dditional hardware resources.