A MICROPOWER CMOS ALGORITHMIC A D A CONVERTER

A low-power and compact VLSI architecture, implementing a bidirectiona l bit-serial A/D/A (analog-to-digital and digital-to-analog) converter , is presented, Both functions of algorithmic D/A conversion and succe ssive approximation AID conversion are combined into a single device, converting bits in the order from most to least significant. The MSB-f irst order guarantees robust implementation, relatively insensitive to component mismatches, offsets and nonlinearities. Also, since the A/D conversion makes use of the intermediate D/A conversion results, matc hed monotonic characteristics are obtained in both directions of conve rsion. The final D/A result is available at the end of A/D conversion, and can be used directly in applications calling for analog quantizat ion. More general use of the A/D/A converter allows for bidirectional read/write digital access to local analog information in VLSI, The rob ust architecture supports dense integration of multiple low-power data conversion units along with digital processors or sensory circuitry i n a standard CMOS process. Minimum sizing of active and passive device s in the implementation, to obtain optimal area and energy efficiency, is limited by clack feedthrough and finite gain considerations rather than matching requirements, Experimental results from a prototype VLS I implementation are given, Including control logic, the A/D/A cell me asures 216 mu m x 315 mu m in a 2-mu m CMOS process, and achieves 8-b untrimmed monotonicity at 200 mu W power consumption for a 20 mu s con version cycle. This corresponds to 4 nJ of energy dissipated per 8-b c onverted sample.