A FUNCTION-PIPELINED ARCHITECTURE AND VLSI CHIP FOR MPEG VIDEO IMAGE-CODING

Authors
WU CM CHOU ZH CHEN YL
Citation
Cm. Wu et al., A FUNCTION-PIPELINED ARCHITECTURE AND VLSI CHIP FOR MPEG VIDEO IMAGE-CODING, IEEE transactions on consumer electronics, 41(4), 1995, pp. 1127-1137
Citations number
8
Categorie Soggetti
Telecommunications,"Engineering, Eletrical & Electronic
Journal title
IEEE transactions on consumer electronics → ACNP
ISSN journal
00983063
Volume
41
Issue
4
Year of publication
1995
Pages
1127 - 1137
Database
ISI
SICI code
0098-3063(1995)41:4<1127:AFAAVC>2.0.ZU;2-R
Abstract
A function-pipelined architecture is presented for MPEG video image co ding. Also, based on a 0.8um SPDM CMOS technology, a VLSI chip has bee n designed and implemented for such an architecture. The chip consists of 43,066 transistors and has a die size of 6,673um x 5,260um (or 0.3 6 cm(2)). In the future, with such a VLSI chip, a coding processor wil l be developed for improving the performance of the MPEG video encodin g system under development.