A DESIGN SYNTHESIS SYSTEM FOR RECURSIVE DSP ALGORITHMS REPRESENTED BYFULLY SPECIFIED FLOW-GRAPHS

This paper describes a design synthesis environment which can generate an efficient VLSI layout from a recursive DSP algorithm specified by a graph. The design synthesis environment is divided into three parts: optimal schedule generation, circuit synthesis, and VLSI layout gener ation (silicon compilation). The scheduler first computes optimality c onditions for a given input algorithm and then finds a schedule which satisfies the optimality conditions. We have employed a cycle-static o ptimal multiprocessor compiler as a scheduler. The circuit synthesis c omponent translates the optimal schedule into a structural specificati on, including the control structures, for an circuit realization. In t he final part, a VLSI layout is generated from the structural specific ation. We have chosen the LAGER system for the silicon compilation. Th is paper illustrates the design synthesis process with complete detail s of a simple, complete example, a second order Direct Form II IIR fil ter.