DESIGN TECHNIQUES FOR FAULT-TOLERANT SYSTOLIC ARRAYS

A systematic approach of designing fault-tolerant systolic architectur es is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by me rging the corresponding systolic array of the three versions of the al gorithm, The merging method attempts to obtain the fault-tolerant syst olic array at minimal cost in terms of area and speed, It is based on rescheduling input data, rearranging data flow, and increasing the uti lization of the array cells. The resulting design can detect and toler ate all single permanent and temporary faults and the majority of the multiple fault patterns with high probability.