CELLULAR LOGIC BUS ARBITRATION

The functional and VLSI design of a novel one-of-N bus arbitration cir cuit for a time-shared bus-interconnected multiprocessor system is pre sented. The proposed system is a multilevel, hierarchical, two-bit cel lular processor structure. The arbitration protocol of rotating priori ty has been customised to produce a hierarchical, fairness-oriented, r otating-priority protocol that guarantees efficient and deadlock-free time sharing of the bus, with better complexity measures compared to b oth rotating- and unequal-priority protocols.