TESTING CHECK BITS AT NO COST IN RAMS WITH ON-CHIP ECC

The paper addresses the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are teste d in parallel with the testing of the information bits. The solution e ntails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults wh ile the information bits are being tested, without any increase in the length of the test sequence. Further, the parity-check matrices are s uch that there is no loss in error-correction capabilities, and there is no penalty in the worst-case delay of the error-correcting logic.