MULTILEVEL LOGIC SYNTHESIS FOR PAL DEVICES

Authors
PEARCE M
Citation
M. Pearce, MULTILEVEL LOGIC SYNTHESIS FOR PAL DEVICES, IEE proceedings. Part E. Computers and digital techniques, 140(6), 1993, pp. 313-319
Citations number
16
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture","Computer Science Theory & Methods
Journal title
IEE proceedings. Part E. Computers and digital techniques → ACNP
ISSN journal
01437062
Volume
140
Issue
6
Year of publication
1993
Pages
313 - 319
Database
ISI
SICI code
0143-7062(1993)140:6<313:MLSFPD>2.0.ZU;2-#
Abstract
A system has been developed to perform multilevel logic synthesis onto PALs for designs that will not fit in two-level sum of products form. The procedure is based upon the application of technology dependent s elective collapse algorithms on a multilevel circuit. The multilevel c ircuit may be obtained using a number of different synthesis strategie s. The packages have been implemented in C and added to SIS, the seque ntial synthesis system developed at Berkeley. Results compare favourab ly with the best previous system known.