STRONGLY FAULT-SECURE DESIGNS FOR ARITHMETIC-ARRAYS

In the paper we make a comparative study of two techniques to design e rror-detectable array architectures. These techniques are the redundan t binary representation (RBR) where the data is encoded in the 1-out-o f-3 code; and the two-rail logic where the data is encoded in the 1-ou t-of-2 code. In recent work, the RBR has been used to achieve online e rror detection and localisation by checking the data on the array bord ers. Here we show that another approach is also possible, with less ha rdware cost, where the checking takes place on the local (processor) l evel. This provides immediate error detection without delay. The perfo rmance of the RBR approaches has been compared with the two-rail appro ach. The results show that the RBR approaches require more hardware ov erheads, for small word lengths (n). However, the hardware cost of the two techniques are approximately the same for large n, while the RBR approaches offer much faster arithmetics for all n.