A BIDIRECTIONAL MOTION COMPENSATION LSI WITH A COMPACT MOTION ESTIMATOR

Citation
N. Hayashi et al., A BIDIRECTIONAL MOTION COMPENSATION LSI WITH A COMPACT MOTION ESTIMATOR, IEICE transactions on electronics, E78C(12), 1995, pp. 1682-1690
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
09168524
Volume
E78C
Issue
12
Year of publication
1995
Pages
1682 - 1690
Database
ISI
SICI code
0916-8524(1995)E78C:12<1682:ABMCLW>2.0.ZU;2-P
Abstract
A motion compensation LSI for realtime MPEG1/H.261 video encoding has been developed. This LSI employs a compact motion estimator that consi sts of vector search array professors. Furthermore, an efficient motio n vector search strategy that enables bidirectional searches with a -1 6.0/+15.5 pels range is adopted to maintain encoded picture quality. T he adopted strategy takes two steps. The first step is the full search for 2-pel precision vectors within the range of +/-16 pels. A 4-to-1 sub-sampling technique with a low pass filter is employed in this step . The second step is the full search for half-pel precision vectors wi thin a +/-1.O pels search range centered on the location pointed by th e best 2-pel precision vectors. This strategy is compared with the exh austive-search strategy. It is shown that the number of operations and external memory access cycles are reduced to 1/11 and 1/2, respective ly, while differences of the signal to noise ratios obtained by simula tion are within 0.2 dB. Those reductions contribute to lowering power dissipation. The array processors calculate the values of distortion. They accumulate the absolute differences between current and reference data with a feedback loop to keep the number of processor elements eq ual to the number of pels in a row of the current block. Multiple refe rence data buses and a delay Line in the feedback loop have been intro duced for efficient calculation. In addition, cascade connection of th e array processors is studied to shorten calculation periods. This LSI controls input frames reordering buffers and reference frames buffers . It generates the prediction and the prediction error blocks as well as the motion vectors. AC power of current blocks and the values of di stortion are obtained for the bit rate control. This LSI is fabricated using 0.8 mu m 2-level metal CMOS technology and dissipates 2.0 W fro m 5 V supply at 36 MHz.