A 600 MW SINGLE-CHIP MPEG2 VIDEO DECODER

This paper describes a 600 mW single-chip MPEG2 video decoder, impleme nted in a 0.5 mu m triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precha rge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read p ower consumption one-third of that of a conventional dual-port RAM. Va rious techniques such as multiple-clock architecture and a system cloc k independent from a display clock make a system clock frequency as lo w as possible. The video decoder has a syntax parser, so that it can h andle the higher syntactic elements of MPEG2 bit streams without any h ost processor and decode the Main profile at Main level of MPEG2 bit s treams.