A 16-BIT DIGITAL SIGNAL PROCESSOR WITH SPECIALLY ARRANGED MULTIPLY-ACCUMULATOR FOR LOW-POWER CONSUMPTION

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Vi terbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations a re so common in digital signal processing, this mechanism can reduce t he average clock frequency of the DSP resulting in lower power consump tion. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles neede d to be executed. The DSP was fabricated using a 0.8 mu m CMOS 2-alumi num layer process technology to integrate 644 K transistors on a 9.30 mm x 9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V V-dd'.