A CIRCUIT LIBRARY FOR LOW-POWER AND HIGH-SPEED DIGITAL SIGNAL PROCESSOR

A new high performance digital signal processor (DSP) that lowers powe r consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device co ntains high performance, hard-wired functionality with a specialized i nstruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features b oth full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply volta ge, even though a power supply voltage in most applications will be sh ifted to 3 V. Several circuits was newly developed to achieve low powe r consumption and high speed operation at both 5 V and 3 V process usi ng the same data base. The device also features over 50 MIPS of proces sing power with low power consumption and 100 nA stand-by current at e ither 3 V or 5 V. One remarkable advantage is a flexible CPU core appr oach for the future spin-off devices with different ROM/RAM configurat ions and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.