SILICON-ON-INSULATOR MATERIAL QUALIFICATION FOR LOW-POWER COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR APPLICATION

Citation
Ma. Mendicino et al., SILICON-ON-INSULATOR MATERIAL QUALIFICATION FOR LOW-POWER COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR APPLICATION, Thin solid films, 270(1-2), 1995, pp. 578-583
Citations number
13
Categorie Soggetti
Physics, Applied","Material Science","Physics, Condensed Matter
Journal title
ISSN journal
00406090
Volume
270
Issue
1-2
Year of publication
1995
Pages
578 - 583
Database
ISI
SICI code
0040-6090(1995)270:1-2<578:SMQFLC>2.0.ZU;2-D
Abstract
To quantify silicon-on-insulator (SOI) material quality with limited o r no processing requires an understanding of the correlations between material properties and device/circuit performance. We have developed robust procedures for on-line and off-line material qualification. Lig ht point-defect detection, total reflectance X-ray fluorescence spectr oscopy, atomic force microscopy, and wafer flatness measurements have been used to non-destructively qualify SOI wafers. Identification of d efects has been performed by coupling scanning electron microscopy (SE M)/optical review and wet chemical etch procedures with surface defect mapping. Some of the most detrimental defects for separation by impla ntation of oxygen (SIMOX) wafers are caused by metal particle contamin ation introduced during implant. Off-line material characterization ha s been performed using transmission electron microscopy, SEM, Auger el ectron spectroscopy, secondary ion mass spectrometry, and wet chemical etch procedures. Buried oxide (BOX) and metal-oxide semiconductor (MO S) capacitors and MOS field effect transistors (MOSFETs) (L(drawn) gre ater than or equal to 0.2 mu m) have been fabricated on 200 mm SOI waf ers for correlation of material properties and device performance. BOX capacitors have been used to detect defects and contamination under t he buried oxide and electrical defects in the buried oxide of SIMOX ma terial. The defects and contamination under the BOX show spatial non-u niformities within wafers that can be correlated with similar non-unif ormities during the implant process. Together, these results have assi sted in defining a material qualification methodology for SOI that is well-aligned with low-power technology.