PARALLEL AND PIPELINED VLSI IMPLEMENTATION OF A STAGED DECODER FOR BCM SIGNALS

This paper is devoted to VLSI implementation of a staged decoder for B lock-Coded Modulation (BCM). We first review a general parallel and pi pelined implementation of the decoder and we identify the parameters t o be considered for optimization. A particular BCM scheme, based on th e 8-PSK signal set, is chosen for a case study. Several ideas are desc ribed leading to a code-optimized design, and hardware implementation is shown, Next, we evaluate the performance of our design. In particul ar it is shown that, by exploiting regularity, a simple structure whic h achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2 mu standard cells CMOS technology. Further optimi zation and simple stacking of ten processors on a single chip in a blo ck-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates).