AN INSTRUCTION SET OPTIMIZATION ALGORITHM FOR PIPELINED ASIPS

This paper proposes a new method to design an optimal pipelined instru ction set processor using a formal HW/SW codesign methodology. A HW/SW partitioning algorithm for selecting an optimal pipelined architectur e is introduced. The codesign task addressed in this paper is to find a set of hardware implemented operations to achieve the highest perfor mance of an ASIP with pipelined architecture under given gate count an d power consumption constraints. The problem formalization as well as the proposed algorithm can be considered as an extension of our previo us work toward a pipelined architecture. The experimental results show that the proposed method is quite effective and efficient.