RECLOCKING CONTROLLERS FOR MINIMUM EXECUTION TIME

In this paper we describe a method for resynthesizing the controller o f a design for a fixed datapath with the objective of increasing the d esign's throughput by minimizing its total execution time. This work h as tremendous potential in two important areas: one, design reuse for retargetting datapaths to new libraries, new technologies and differen t bit-widths; and two, back-annotation of physical design information during High-Level Synthesis (HLS), and subsequent adjustment of the de sign's schedule to account for realistic physical design information w ith minimal changes to the datapath. We present our approach using var ious formulations, prove optimality of our algorithm and demonstrate t he effectiveness of our technique on several HLS benchmarks. We have o bserved improvements of up to 34% in execution time after straightforw ard application of our controller resynthesis technique to the outputs of HLS.