A 35 NS CYCLE TIME 3.3 V ONLY 32 MB NAND FLASH EEPROM

Authors
IWATA Y IMAMIYA K SUGIURA Y NAKAMURA H OODAIRA H MOMODOMI M ITOH Y WATANABE T ARAKI H NARITA K MASUDA K MIYAMOTO J
Citation
Y. Iwata et al., A 35 NS CYCLE TIME 3.3 V ONLY 32 MB NAND FLASH EEPROM, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1157-1164
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
30
Issue
11
Year of publication
1995
Pages
1157 - 1164
Database
ISI
SICI code
0018-9200(1995)30:11<1157:A3NCT3>2.0.ZU;2-O
Abstract
A 32 Mb NAND type flash EEPROM has been developed with 0.425 mu m CMOS technology, A 35 ns cycle time is achieved by adopting a pipeline sch eme, A boosted word-line scheme and a program verify operation achievi ng tight threshold voltage (V-th) distribution of programmed cells red uce read-out access time, Multiple block erase operation is realized b y adopting erase block registers. All functions are operable with a si ngle 3.3 V. or 5 V power supply.