AN EXPERIMENTAL 220-MHZ 1-GB DRAM WITH A DISTRIBUTED-COLUMN-CONTROL ARCHITECTURE

A distributed-column-control architecture is proposed to reduce the bu rst-mode cycle time of large-capacity DRAM's. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing dif ference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing ma rgin between the activation of column selection lines, reducing the cy cle time by 25%. To evaluate this architecture, an experimental synchr onously operating l-Gb DRAM was designed and fabricated using a 0.16-m u m CMOS process, It operates with a 220-MHz clock and a 1.5-V power s upply.