A 300-MHZ 4-MB WAVE-PIPELINE CMOS SRAM USING A MULTIPHASE PLL
Citation
K. Ishibashi et al., A 300-MHZ 4-MB WAVE-PIPELINE CMOS SRAM USING A MULTIPHASE PLL, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1189-1195
Categorie Soggetti
Engineering, Eletrical & Electronic
SICI code
0018-9200(1995)30:11<1189:A34WCS>2.0.ZU;2-P
Abstract
A 4-Mb (64k x 64) synchronous wave-pipeline CMOS SRAM is fabricated by
0.25-mu m CMOS technology, Multiphase active pulse control (MPAC) ena
bles fully random 300 MHz operation at 2.5 V, resulting in a bandwidth
of 2.4 GB/s, The pulse is generated by multiphase PLL (MPPLL) using a
n array oscillator with current consumption of 7.5 mA.
