A 1 NS, 1 W, 2.5 V, 32 KB NTL-CMOS SRAM MACRO USING A MEMORY CELL WITH PMOS ACCESS TRANSISTORS

While an ECL-CMOS SRAM can achieve both ultra high speed and high dens ity, it consumes a lot of power and cannot be applied to low power sup ply voltage applications, This paper describes an NTL (Non Threshold L ogic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS m emory cell, an NTL decoder with an on-chip voltage generator, and an a utomatic bit line signal voltage swing controller, A 32 Kb SRAM macro, which achieves al ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 mu m BiCMOS technology.