A 300-MHZ 64-B QUAD-ISSUE CMOS RISC MICROPROCESSOR

This 300 MHz quad-issue custom VLSI implementation of the Alpha archit ecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint9Z, an d 512 SPECfp92. The 16.5 mm x 18.1 mm die contains 9.3 M transistors a nd dissipates 50 W at 300 MHz, It is fabricated in a 3.3 V, four-layer metal, 0.5 mu m, CMOS process. The upper metal layers (metal-3 and me tal-4) are primarily used for power, ground, and clock distribution, T he chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin c eramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dua l-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, write-back cache, This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency.