A 64-B MICROPROCESSOR WITH MULTIMEDIA SUPPORT

A 167 MHz 64 b VLSI CPU chip is described. The chip executes a 333-MFL OPS (peak) with an estimated system performance of 270SPECint92/380SPE Cfp92 (@167 MHz, 2 MB E-cache). The 17.7 x 17.8 mm die is fabricated w ith a 0.5 micron CMOS technology with four metal layers and contains 5 .2 M transistors. The superscalar processor is capable of sustaining a n execution rate of four instructions per cycle even in the presence o f conditional branches and cache misses. Four fully pipelined 8 x 16 b multipliers and four single-cycle latency 16 b adders combine to spee d up image processing, 2-D, 3-D graphics, video compression/decompress ion by up to an order of magnitude. High clock speed was obtained by t he use of delayed reset logic, a new register file design, and novel c omparators. Strict design methodology allowed fully functional first s ilicon which met all speed targets. The power dissipation of the chip is 28 W.