CLOCK BUFFER CHIP WITH MULTIPLE-TARGET AUTOMATIC SKEW COMPENSATION

This paper describes the application of a digital delay locked loop th at compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASIC's, For a co mputer system consisting of nine PC boards (''modules'') plugged into a back plane with two clock chips per board and six ASIC's per clock c hip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns.