A 1-GB DRAM FOR FILE APPLICATIONS

A time-shared offset-canceling sensing scheme, a defective word-line H i-Z standby scheme, and a flexible multi-macro architecture have been developed for l-Gb DRAM. These circuit technologies have been applied to a l-Gb DRAM for file applications employing 0.25 mu m CMOS process technology, a diagonal bit-line fell, and a two-stage pipeline circuit technique, In this DRAM, a 30% chip size reduction and a 400-MB/s dat a transfer rate have been achieved. A 100% improvement in yield has be en estimated by Monte-Carlo simulation, The l-Gb DRAM die size is 936 mm(2). The cell size is 0.54 mu m(2). The operating current is 68 mA a t 2 V and 100 MHz.