A 1.6 GBYTE S DATA TRANSFER RATE 8 MB EMBEDDED DRAM/

Authors
MIYANO S NUMATA K SATO K YABE T WADA M HAGA R ENKAKU M SHIOCHI M KAWASHIMA Y IWASE M OHGATA M KUMAGAI J YOSHIDA T SAKURAI M KAKI S YANAGIYA N SHINYA H FURUYAMA T HANSEN P HANNAH M NAGY M NAGARAJAN A RUNGSEA M
Citation
S. Miyano et al., A 1.6 GBYTE S DATA TRANSFER RATE 8 MB EMBEDDED DRAM/, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1281-1285
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
30
Issue
11
Year of publication
1995
Pages
1281 - 1285
Database
ISI
SICI code
0018-9200(1995)30:11<1281:A1GSDT>2.0.ZU;2-Y
Abstract
An 8 Mb embedded DRAM has been developed. The salient feature of this embedded DRAM is page fault tolerance, Accessing across different page s can be performed using a minimum column cycle, This feature is achie ved by placing a data latch and a transfer gate between the bit line s ense amlifier and the column select gate, This DRAM can be reconfigure d as separated 2 Mb units when it is embedded as a macro cell of an AS IC library.