ASYMPTOTIC LIMITS OF VIDEO SIGNAL-PROCESSING ARCHITECTURES

This paper analyzes the effects of technology scaling on Video Signal Processing (VSP) architectures, We evaluate the processor, the memory, and the interconnect delays in terms of sophisticated delay models (t hat take into account deep-sub-micron device characteristics) and stud y how the response times of these logic components are affected when t he feature sizes scale down, Equations for gate and interconnect delay s, as functions of process scaling, are derived and the impact of thes e results examined in the context of heavily pipelined architectures, architectures featuring crossbar interconnection networks, and archite ctures whose performance is dominated by memory bandwidth, Architectur al parameters such as clock skew, clock frequency, memory interleaving , memory efficiency, and average waiting times are analyzed in the lig ht of the sealing behaviors of the gate and the interconnect delays. I n the context of scaling of interconnection lines and memory modules, we also highlight how the transmission-line characteristics of long li nes are affected by technology scaling and how the delay associated wi th the memory subsystem-both the memory interleaving and the memory in terconnect network-can be a potential bottleneck for the system's spee d of operation, It is likely that sophisticated compilation and schedu ling techniques must be employed along with architectural optimization s to achieve maximum system performance and ensure that the final hard ware-software configuration does not overload the processor-memory com munication.