PLASTIC PACKAGING AND BURN-IN EFFECTS ON IONIZING DOSE-RESPONSE IN CMOS MICROCIRCUITS

Results are reported from an investigation of the effects of packaging and burn-in on the post-irradiation performance of National Semicondu ctor 54AC02 Quad 2-input NOR gates. The test population nias drawn fro m a single wafer fabricated in the National process qualified under Mi l-Prf-38535 to an ionizing radiation hardness of 100 krads(Si). The te st sample was divided between plastic and ceramic packages. Additional ly, half of the plastic samples and half of the ceramic samples receiv ed a 168 hour/125 degrees C burn-in. Tno irradiation schemes were used . The first followed Mil-Std-883 Method 1019.4 (dose rate = 50 rads(Si )/s). The second used a ion, dose rate (0.1 rads(Si)/s). AC. DC, trans fer function and functional behavior were monitored throughout the tes ts. Significant differences among the package types and burn-in variat ions were noted with the plastic, burned-in components demonstrating e nhanced degradation. They how the worst post-irradiation parameter val ues as well as very broad post-irradiation parameter distributions. De gradation is highly dependent upon dose rate and anneal conditions. Tw o different radiation induced leakage paths have been identified, and their characteristics have been correlated to variations in high dose rate and low dose rate circuit performance; Caution is recommended for system developers to ensure that radiation hardness characterization is performed for the same package/burn-in configuration to be used in the system.