EVALUATION OF THE UPSET RISK IN CMOS SRAM THROUGH FULL 3-DIMENSIONAL SIMULATION

Upsets caused by incident heavy ion on CMOS static RAM are studied her e. Three dimensional device simulations, based on a description of a f ull epitaxial CMOS inverter, and experimental results are reported for evaluation of single and multiple bit error risk. The particular infl uences of hit location and incidence angle are examined.