ELIMINATION OF CHARGE-ENHANCEMENT EFFECTS IN GAAS-FETS WITH A LOW-TEMPERATURE-GROWN GAAS BUFFER LAYER

The use of a low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnit ude. This reduction in collected charge is associated with the efficie nt reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated c ircuits will be reduced by several orders of magnitude when compared t o conventional FET-based GaAs ICs.